INDUSTRY READY PROFESSIONAL TRAINING (IRPT) IN VLSI DESIGN/EMBEDDED SYSTEM DESIGN

PROGRAM INFO(VLSI Design-VLSID/Embedded System Design-ESD)

    1. VEDA IIT offers Industry Ready Professional Training in VLSI DESIGN/EMBEDDED SYSTEM DESIGN, which is JNTUH-approved.
    2.The training program fulfills coursework for 2 semesters of B.Tech, 4th year of JNTUH Constituent, Affiliated, and Autonomous Colleges.
    3. JNTUH approved the transfer of 40 credits earned at VEDA IIT for the award of a B.Tech degree.
    4. Internship is provided in second semester in VEDA IIT/Consortium company (terms and conditions apply)

    Course structure

    IV Year I Semester

     

    S. No.

    Type

    Course Code

    Course Title

    1

    T

    V157AA

    Advanced Logic Design with Functional Blocks & State Machines

    2.

    E3

    V157AB

    Unix & Scripting Languages

    3.

    E4

    Choose one of the following:

    V157AC

    1. VLSI Design with Verilog

    V157AD

    2. X86 Architecture

    4.

    OE2

    Choose one of the following:

    V157AE

    1. C++ & Verification Methodologies

    V157AF

    2. Physical Design Basics

    V157AG

    3. C++, Data Structures in C

    5.

    L

    V15701

    Unix & Scripting Languages Laboratory

    6.

    EL

    Choose one of the following Lab:

    V15702

    1. VLSI Verilog & System Verilog Laboratory

    V15703

    2. VLSI Physical Design Laboratory

    V15704

    3. C++, Data Structures in C Laboratory

    V15705

    4. X86 Laboratory

    7.

    PS1

    V15706

    Project Stage – I

     

    IV Year II Semester

     

    S. No.

    Course

    Course Title

    1

    E5

    Choose one of the following:

    V158AA

    1. VLSI Synthesis

    V158AB

    2. Real Time operating system

    2

    E6

    Choose one of the following:

    V158AC

    1. System Verilog Assertions and UVM

    V158AD

    2. Low Power Physical Design & Chip Finishing

    V158AE

    3. Advanced Processor Architecture

    V158AF

    4. Introduction to Web Development

    3

    OE3

    Choose one of the following:

    V158AG

    1. Design for Testability (DFT)

    V158AH

    2. ARM Architecture and Interface Protocols

    V158AJ

    3. Core JAVA

    V158AK

    4. Full Stack

    4

    S

    V15801

    Seminar

    5

    PS2

    V15802

    Project Stage -II

     

     

    Program Logistics

    • Full Time, 6 days per week
    • Lecture Sessions 3 hours per day
    • Lab & Design Practice 5 hours per day
    • 8:30am-9:00am: Student preparation
    • 9:00am-10:30am: Morning Lecture
    • 10:30am-01:00pm: lab /Assignment (with Tea Break)
    • 01:00pm-01:30pm: Lunch Break
    • 01:30pm-03:00pm: Afternoon Lecture
    • 03:00pm-06:00pm: lab /Assignment (with Tea Break)