Careers in VLSI Design - Digital

Logic Design (LD)/ Logic Verification (LV)/ Design Verification (DV)/ Logic Implementation (LI)/ DFT

PROGRAM INFO(VLSI Design – Digital)

Program Duration

The program is offered in two different durations based on requirements, as indicated in the advertising posters.

  • Program-1 with 6-Month duration: Includes training along with project work.
  • Program-2 with 1-Year duration: Consists of 6 months of training followed by a 6-month internship. Stipend will be provided during internship.

Training Fees

  • Sponsored Training: The entire training fee will be covered by the sponsoring company for candidates who have opted for sponsored training. However, the candidate must agree to the terms and conditions set by the sponsoring company.
  • Self-Sponsored Training: In special cases when it is provided as an option in the poster. The candidates who have chosen this option are required to pay the applicable training fees themselves.

Program Contents LD/ LV/ DV/ LI/ DFT

Common

  • Number systems
  • Combinational circuit designs at gate and functional block level both for functionality and timing
  • Sequential circuit elements, timing and Simple circuit designs for functionality and for timing
  • OS: Unix
  • Programming: C
  • Scripting: PERL/Python, TCL
  • Verilog HDL

Domain specific

  1. Logic Design (LD Domain)
    • Advanced state machine concepts
    • Synchronizers & Clock Domain Crossing (CDC)
    • Design of bigger combinational and sequential functional blocks
    • More complex state machines in Verilog
  2. Logic Verification (LV Domain)/ Design Verification (DV Domain)
    • Programming: C++
    • System Verilog: Classes, constraints, randomization, Assertions, Functional coverage
    • Universal Verification Methodology (UVM): Objects and components, UVM factory, UVM phases
  3. Logic Implementation (LI Domain) / DFT
    • Synthesis: Design Rule Constraints (DRCs), STA for single and multi clock designs, Timing exceptions, Compilation strategies
    • Design For Testability (DFT): Fault models, Scan insertion and Testing, Compression and de-compression, Boundary scan, Hierarchical DFT

Program Logistics

  • Full Time, 6 months, 6 days per week
  • Lecture Sessions 3 hours per day
  • Lab & Design Practice 5 hours per day
  • 8:30am-9:00am: Student preparation
  • 9:00am-10:30am: Morning Lecture
  • 10:30am-01:00pm: lab /Assignment (with Tea Break)
  • 01:00pm-01:30pm: Lunch Break
  • 01:30pm-03:00pm: Afternoon Lecture
  • 03:00pm-06:00pm: lab /Assignment (with Tea Break)

 

Minimum Qualification for “Engineer Trainee” position

  • Eligibility: B.E./B.Tech/ M.Sc. in Electronics/ Electrical/ Instrumentation
  • Candidates who are in the final semester are also eligible, provided they have no backlogs to date and no remaining classwork in their last semester at their college/university.
  • Percentage: 65%

Minimum Qualification for “Jr. Engineer Trainee” position

  • Eligibility: Diploma in Electronics/ Electrical/ Communications/ IE or B.Sc. in Electronics
  • Percentage: 65%

LD / LV/ DV / LI/ DFT