Program Information IN Logic Design/ LOGIC Verification/ LOGIC Implementation

PROGRAM INFO(Logic Design – LD/ Logic Verification – LV/ Design Verification – DV/ Logic Implementation – LI/ DFT)

Common

Number systems
Combinational circuit designs at gate and functional block level both for functionality and timing
Sequential circuit elements, timing and Simple circuit designs for functionality and for timing
OS: Unix
Programming: C
Scripting: PERL/Python, TCL
Verilog HDL

Domain specific

Logic Design (LD Domain)
- Advanced state machine concepts
- Synchronizers & Clock Domain Crossing (CDC)
- Design of bigger combinational and sequential functional blocks
- More complex state machines in Verilog
Logic Verification (LV Domain)/ Design Verification (DV Domain)
- Programming: C++
- System Verilog: Classes, constraints, randomization, Assertions, Functional coverage
- Universal Verification Methodology (UVM): Objects and components, UVM factory, UVM phases
Logic Implementation (LI Domain) / DFT
- Synthesis: Design Rule Constraints (DRCs), STA for single and multi clock designs, Timing exceptions, Compilation strategies
- Design For Testability (DFT): Fault models, Scan insertion and Testing, Compression and de-compression, Boundary scan, Hierarchical DFT