PROGRAM INFORMATION(VLSI Logic Design) 
Program Contents
- Introduction to Number system
- Advanced Digital Design concepts
- Coding designs in Verilog RTL and simulation
- Unix Operating System, Shell Programming & VI Editor
- Introduction to C & C++ Programming Languages
- Advanced Scripting languages: PERL, TCL
- Introduction to Synthesis
- Introduction to Design For Test (DFT) – Scan, ATPG & JTAG Concepts (Institute Optional)
- Introduction to Verification using System Verilog (Institute Optional)
- Concepts of Static timing analysis (STA)
- Transferable skills (Institute Optional)
Program Logistics
- Full Time, 6 months, 6 days per week
- Lecture Sessions 3 hours per day
- Lab & Design Practice 5 hours per day
- 8:30am-9:00am: Student preparation
- 9:00am-10:30am: Morning Lecture
- 10:30am-01:00pm: lab /Assignment (with Tea Break)
- 01:00pm-01:30pm: Lunch Break
- 01:30pm-03:00pm: Afternoon Lecture
- 03:00pm-06:00pm: lab /Assignment (with Tea Break)
