Job Description (VLSI Design – Digital)
Job Description – Logic Design
Logic Design is the front-end activity of a chip design which involves essentials of digital design, Verilog behavioral & RTL design.
- Work on understanding the specifications and converting the specifications to RTL
- Work on RTL simulations and debug failures
- Understand the various interface logic blocks, clocking schemes and integrate the blocks into a SOC
- Work with pre-silicon verification teams to debug the root cause for RTL design issues and failures
- Ability to automate the design process to improve efficiency
- Exhibit strong analytical and excellent communication skills, conceptual understanding, and attention to detail
Job Description – Logic Verification/ Design Verification
Logic Verification is to check the correct behavior of a given circuit against its specification.
- Develop test cases and test stimulus to verify the design
- Create verification environments in System Verilog, UVM, C/C++
- Interacts with logic design engineers and architects to understand the specification and come up with the verification scenarios
- Work on understanding the SOC application and use cases to create comprehensive test plans for each functional feature
- Work on gate level simulations and debug failures
- Gain critical knowledge on various protocols like I2C/UART/SPI/PCIe/USB etc.
- Ability to automate the verification process, regression testing and data analysis
- Exhibit strong analytical and excellent communication skills, conceptual understanding, and attention to detail
Job Description – Logic Implementation/ DFT
Logic Implementation involves synthesis and DFT where synthesis transforms RTL design into a gate-level netlist and DFT is an innovative design technique to make testing a chip cost-effective.
- Specify various constraints on the netlist, analyze Design Rule Constraints (DRCs), timing analysis of various timing paths and timing exceptions
- Work on bottom-up synthesis of hierarchical designs
- Generate the patterns to identify various faults in the design
- Insert the test logic and generate the patterns to detect the fault
- Work on understanding the various types of manufacturing defects that manifest during fabrication of the SOC and generate patterns to identify the same
- Understand the trade-offs for test time, test pattern size and test requirements
- Insert the JTAG TAP controller, test logic and test controls hierarchically into SOC design and run DFT design rule checks and analyze coverage reports
- Develop test patterns to test the SRAM memories, logic and GPIO using industry standard EDA tools
- Work closely with ATE test/Product engineering teams to bring up test patterns and debug post silicon issues
- Develop DFT mode timing constraints for physical design team to perform timing sign-off
- Exhibit strong analytical and excellent communication skills, conceptual understanding, and attention to detail
Minimum Qualification
- Eligibility: B.E./B.Tech/ M.Sc. in Electronics/ Electrical/ Instrumentation
- Percentage: 65%