Course Syllabus

COURSE SYLLABUS (JNTUK)

Semester 1

S.No

Name of the Subject

Theory

 

1

Contemporary  Logic Design

2

Verilog and C++

3

UNIX, C Programming and Scripting  languages

 

Elective-I

4

X86 Processor – Architecture , Programming and Interfacing

VLSI Physical Design Essentials

Labs

 

5

VLSI Verilog Design Laboratory

6

VLSI Verilog Verification and C++  Laboratory

7

Unix & C Programming Laboratory

8

Scripting Languages Laboratory

 

Elective-II

9

X86 Processor – Architecture & Programming Laboratory

VLSI Physical Design Essentials Laboratory

 

Semester 2

S.No

Name of the Subject

Theory

 

1

Synthesis & Formal Verification

2

Processor System Architecture

3

Design for Testability

 

Elective-III

4

System Verilog Test benches Using UVM

VLSI Advanced Physical Design

Labs

 

5

Synthesis and Formal Verification Laboratory

6

Processor System Architecture Laboratory

7

Design for Testability Laboratory

 

Elective-IV

8

System Verilog Test benches Using UVM Laboratory

VLSI Advanced Physical Design Laboratory

 

Semester 3

S.No

Name of the Subject

1

Comprehensive Viva -Voce

2

Seminar – I

3

Project work Part – I

 

Semester 4

S.No

Name of the Subject

1

Seminar – II

2

Project work Part – II