Course Syllabus

COURSE SYLLABUS (JNTUH)

Semester 1

S.No

Category

Course Title

1

Core Theory-1

Contemporary  Logic Design

2

Core Theory -2

Verilog and C++

3

Core Theory -3

Programming and Scripting  languages

4

Elective Theory -1

VLSI Analog Design

VLSI Physical Design Essentials

5

Core Lab -1

VLSI Verilog Design Lab.

6

Core Lab -2

VLSI Verilog Verification and C++  Lab.

7

Core Lab -3

Unix & C Programming Lab.

8

Core Lab -4

Scripting Languages Lab.

9

Elective Lab -1

VLSI Analog Design Lab.

VLSI Physical Design Essentials Lab.

Semester 2

S.No.

Category

Course Title

1

Core Theory -4

Synthesis & Formal Verification

2

Core Theory -5

Processor System Architecture

3

Elective Theory -2

Analog Mixed Signal Design

System Verilog Test benches Using UVM

VLSI Advanced Physical Design

4

Elective Theory -3

High Speed CMOS Design

Design for Testability – Logic Design

Design for Testability – Physical Design

5

Core Lab -5

Synthesis and Formal Verification Lab.

6

Core Lab -6

Processor System Architecture Lab.

7

Elective Lab -2

Analog Mixed Signal Design  Lab.

System Verilog Test benches Using UVM Lab.

VLSI Advanced Physical Design Lab.

8

Elective Lab  -3

High Speed CMOS Design Lab.

Design for Testability Lab. – Logic Design.

Design for Testability Lab. – Physical Design

Semester 3

S.No

Category

Course Title

1

 

Comprehensive Viva -Voce

2

 

Seminar 1

3

 

Project work Stage 1 &  Progress review 1

 

Semester 4

S.No

Category

Course Title

1

 

Seminar 2

2

 

Project work Stage 2 &  Progress review 2

3

 

Project Evaluation(Viva-Voce)