Careers in VLSI Design - Digital

Physical Design (PD)/ Physical Verification (PV)

PROGRAM INFO(VLSI Design – Digital)

Program Duration

The program is offered in two different durations based on requirements, as indicated in the advertising posters.

  • Program-1 with 6-Month duration: Includes training along with project work.
  • Program-2 with 1-Year duration: Consists of 6 months of training followed by a 6-month internship. Stipend will be provided during internship.

Training Fees

  • Sponsored Training: The entire training fee will be covered by the sponsoring company for candidates who have opted for sponsored training. However, the candidate must agree to the terms and conditions set by the sponsoring company.
  • Self-Sponsored Training: In special cases when it is provided as an option in the poster. The candidates who have chosen this option are required to pay the applicable training fees themselves.

Program Contents PD/ PV

Common

  • Number systems
  • Combinational circuit design at gate and functional block level both for functionality and timing
  • Sequential circuit elements, timing and Simple circuit Design for functionality and for timing
  • OS: Unix
  • Scripting: PERL/Python, TCL
  • Introduction to MOSFETs, Schematic fundamentals, stick diagrams, Basic layout Design, Introduction to Physical DRC & LVS, PD Flow

Domain specific

  1. Physical Design (PD domain)

     

    • PD overview, timing DRCs (Design Rule Constraints) & STA basics
    • Floor Plan, Power Plan, Placement, CTS & Routing
    • Parasitic extraction techniques, SI Analysis, IR/EM Analysis & Physical Verification basics
  2. Physical Verification (PV Domain)

     

    • Physical Verification Flow
    • PV Checks: Layout Versus Schematic(LVS), Design Rule Check(DRC) & Antenna, ERC, design-for-manufacturing (DFM) & design-for-yield (DFY), and Pattern matching & fixes

Program Logistics

  • Full Time, 6 months, 6 days per week
  • Lecture Sessions 3 hours per day
  • Lab & Design Practice 5 hours per day
  • 8:30am-9:00am: Student preparation
  • 9:00am-10:30am: Morning Lecture
  • 10:30am-01:00pm: lab /Assignment (with Tea Break)
  • 01:00pm-01:30pm: Lunch Break
  • 01:30pm-03:00pm: Afternoon Lecture
  • 03:00pm-06:00pm: lab /Assignment (with Tea Break)

 

Minimum Qualification for “Engineer Trainee” position

  • Eligibility: B.E./B.Tech/ M.Sc. in Electronics/ Electrical/ Instrumentation
  • Candidates who are in the final semester are also eligible, provided they have no backlogs to date and no remaining classwork in their last semester at their college/university.
  • Percentage: 65%

Minimum Qualification for “Jr. Engineer Trainee” position

  • Eligibility: Diploma in Electronics/ Electrical/ Communications/ IE or B.Sc. in Electronics
  • Percentage: 65%

PD / PV