PROGRAM INFORMATION(Physical Design – PD/ Verification – PV)

Program Contents PD/ PV


  • Number systems
  • Combinational circuit design at gate and functional block level both for functionality and timing
  • Sequential circuit elements, timing and Simple circuit Design for functionality and for timing
  • OS: Unix
  • Scripting: PERL/Python, TCL
  • Introduction to MOSFETs, Schematic fundamentals, stick diagrams, Basic layout Design, Introduction to Physical DRC & LVS, PD Flow

Domain specific

  1. Physical Design (PD domain)

    • PD overview, timing DRCs (Design Rule Constraints) & STA basics
    • Floor Plan, Power Plan, Placement, CTS & Routing
    • Parasitic extraction techniques, SI Analysis, IR/EM Analysis & Physical Verification basics
  2. Physical Verification (PV Domain)

    • Physical Verification Flow
    • PV Checks: Layout Versus Schematic(LVS), Design Rule Check(DRC) & Antenna, ERC, design-for-manufacturing (DFM) & design-for-yield (DFY), and Pattern matching & fixes

Program Logistics

  • Full Time, 6 months, 6 days per week
  • Lecture Sessions 3 hours per day
  • Lab & Design Practice 5 hours per day
  • 8:30am-9:00am: Student preparation
  • 9:00am-10:30am: Morning Lecture
  • 10:30am-01:00pm: lab /Assignment (with Tea Break)
  • 01:00pm-01:30pm: Lunch Break
  • 01:30pm-03:00pm: Afternoon Lecture
  • 03:00pm-06:00pm: lab /Assignment (with Tea Break)