PROGRAM INFO(VLSI Design – VLSID/ Embedded System Design – ESD)
Program Contents
Common
- Number systems
- Combinational circuit designs at gate and functional block level both for functionality and timing
- Sequential circuit elements, timing and Simple circuit designs for functionality and for timing
- OS: Unix
- Programming: C
- Scripting: PERL/Python, TCL
- Verilog HDL
Domain specific
- Design Verification (DV Domain)
- Programming: C++
- System Verilog: Classes, constraints, randomization, Assertions, Functional coverage
- Universal Verification Methodology (UVM): Objects and components, UVM factory, UVM phases
- Physical Design (PD domain)
- PD overview, timing DRCs (Design Rule Constraints) & STA basics
- Floor Plan, Power Plan, Placement, CTS & Routing
- Parasitic extraction techniques, SI Analysis, IR/EM Analysis & Physical Verification basics
- Design Implementation
- Synthesis: Design Rule Constraints (DRCs), STA for single and multi clock designs, Timing exceptions, Compilation strategies
- Design For Testability (DFT): Fault models, Scan insertion and Testing, Compression and de-compression, Boundary scan, Hierarchical DFT
- Embedded Software Development
- CISC/RISC Processor Architecture fundamentals
- 8086 Processor architecture overview
- 8051 Microcontroller overview
- ARM Processor architecture overview
- Standard IO interfaces, peripheral controllers
- RTOS Concepts
- Basics of driver development
- Application Software Development
- Java Script, AJAX, jQuery and HTML/CSS
- Java programming Servlets, Struts & Jsp
- Core PHP
- Database – MySQL & ORACLE
- Mobile Application Development (Android)
Program Logistics
- Full Time, 6 months, 6 days per week
- Lecture Sessions 3 hours per day
- Lab & Design Practice 5 hours per day
- 8:30am-9:00am: Student preparation
- 9:00am-10:30am: Morning Lecture
- 10:30am-01:00pm: lab /Assignment (with Tea Break)
- 01:00pm-01:30pm: Lunch Break
- 01:30pm-03:00pm: Afternoon Lecture
- 03:00pm-06:00pm: lab /Assignment (with Tea Break)