RECRUITMENT OF VEDA FACULTY / LAB ENGINEERS

Job Description: Teaching, Research & Training

Eligibility: BE/B.Tech. & ME/M.Tech./MS in relevant branch (ECE/EEE/EIE) with 1st class or equivalent either in BE/B.Tech. or ME/M.Tech./MS.

Preference will be given to IIT/NIT graduates

No screening test for teachers with minimum 10 years of experience.

Salary: Negotiable

Training: The selected candidates will be provided 6 months of knowledge intensive, industry-oriented full-time training based on requirement.

Location: Hyderabad & Amaravathi

Duration: 3 Hours

Job Domain & Description

Test Pattern

Topics & Syllabus for the test

Marks#

Sample Questions

VLSI Digital Engineering

Logic Design

Digital Design, RTL Implementation, Verification, Synthesis, DFT & Emulation

Physical Design

Physical Placement & Routing, Functional Equivalence, Timing Closure and Design Rule Check

Number Systems, General Electronics, Combinational & Sequential circuits	70
Aptitude	30

Analog Design

Analog circuit design, Spice simulation and Verilog A modeling

Custom layout design

Analog/Custom circuit layout, Layout verification

General Electronics & Circuit Basics	30
Analog Design	70

Embedded Software, Firmware, Drivers and Applications Development, HW/Board Design, Silicon Validation & Characterization

General Electronics, Number Systems, Micro processors & Microcontrollers	50
C- Programming	20
Aptitude	30

Program development in Unix, C, C++, PERL, TCL, Java, Data Structures

*Eligibility: BE/B.Tech. & ME/M.Tech./MS in relevant branch (ECE/EEE/EIE/CSE) with 1st class or equivalent either in BE/B.Tech. or ME/M.Tech./MS.

#Marks may vary slightly.