Careers in VLSI Design - Analog

Custom Layout Design (CLD)

PROGRAM INFORMATION(Custom Layout Design)

Program Duration

The program is offered in two different durations based on requirements, as indicated in the advertising posters.

  • Program-1 with 6-Month duration: Includes training along with project work.
  • Program-2 with 1-Year duration: Consists of 6 months of training followed by a 6-month internship. Stipend will be provided during internship.

Training Fees

  • Sponsored Training: The entire training fee will be covered by the sponsoring company for candidates who have opted for sponsored training. However, the candidate must agree to the terms and conditions set by the sponsoring company.
  • Self-Sponsored Training: In special cases when it is provided as an option in the poster. The candidates who have chosen this option are required to pay the applicable training fees themselves.

Program Contents

Common

  • Number systems
  • Combinational and Sequential circuit design at gate and functional block level and their stick diagrams
  • Fabrication process
  • OS: Unix
  • Scripting: PERL/Python, TCL
  • Basic device physics: Introduction to MOSFETs, regions of operation, Short channel effects, FDSOI and FinFET device explanations.
  • Analog layout concepts: Devices, Matching, layout dependent effects, EM, Antenna effect, Latch-up, Reliability etc.

Domain specific

  1. Standard cell layout design

     

    • Design of layout for digital cells in 9T, 8T library along with PV checks (DRC, LVS, DFM, PM etc.)
  2. Analog layout design

     

    • Circuit explanations for analog circuits such as OPAMP, BGR
    • Layout constraints and guidelines to design circuits with PV checks (LVS, DRC)
  3. Memory Layout design

     

    • Circuit explanations for circuits such as level shifter, sense amplifier
    • Layout constraints and guidelines to design circuits with PV checks (LVS, DRC)

Program Logistics

  • Full Time, 6 months, 6 days per week
  • Lecture Sessions 3 hours per day
  • Lab & Design Practice 5 hours per day
  • 8:30am-9:00am: Student preparation
  • 9:00am-10:30am: Morning Lecture
  • 10:30am-01:00pm: lab /Assignment (with Tea Break)
  • 01:00pm-01:30pm: Lunch Break
  • 01:30pm-03:00pm: Afternoon Lecture
  • 03:00pm-06:00pm: lab /Assignment (with Tea Break)

 

Minimum Qualification for “Engineer Trainee” position

  • Eligibility: B.E./B.Tech/ M.Sc. in Electronics/ Electrical/ Instrumentation
  • Candidates who are in the final semester are also eligible, provided they have no backlogs to date and no remaining classwork in their last semester at their college/university.
  • Percentage: 65%

Minimum Qualification for “Jr. Engineer Trainee” position

  • Eligibility: Diploma in Electronics/ Electrical/ Communications/ IE or B.Sc. in Electronics
  • Percentage: 65%

CUSTOM LAYOUT