Job Description (VLSI Design – Digital)

Minimum Qualification for “Engineer Trainee” position

• Eligibility: B.E./B.Tech/ M.Sc. in Electronics/ Electrical/ Instrumentation
• Candidates who are in the final semester are also eligible, provided they have no backlogs to date and no remaining classwork in their last semester at their college/university.
• Percentage: 65%

Minimum Qualification for “Jr. Engineer Trainee” position

• Eligibility: Diploma in Electronics/ Electrical/ Communications/ IE or B.Sc. in Electronics
• Percentage: 65%

Job Description – Physical Design

Physical design is a process of converting logical connectivity of cells (netlist) into physical connectivity (manufactural layout) meeting power, performance and area requirements. All design components are instantiated with their geometric shapes and have appropriate routing connections in metal layers.

• Validating inputs, Die size estimation, IO placement planning, Floor planning, power planning, placement, CTS, Routing, ECOs, timing sign-off
• Work on implementing the SOC design into manufactural format (GDS) in various silicon technologies
• Understand the Clocking and data flow of blocks and SOC to come up with an optimized floor plan for the design
• Intelligently solve the critical congestion and performance issues in the design by working with logic design engineers
• Perform timing analysis and electrical analysis on the design to ensure the design meets performance and power targets of the end product
• Ability to automate the design process utilizing industry-standard EDA tools to improve efficiency, and analyze results
• Exhibit strong analytical and excellent communication skills, conceptual understanding, and attention to detail

Job Description – Physical Verification

Physical verification is a process of verification of correct electrical and logical functionality, manufacturability, and yield in IC layout using EDA tools.

• Perform various types of physical verification checks (such as LVS, DRC & Antenna, ERC, design-for-manufacturing & design-for-yield, and Pattern matching) at the chip and block level
• Collaborate with the CAD/Technology teams for flow bring up and validation.
• Work directly with the implementation team during the entire chip design cycle to drive signoff closure for tape-out
• Automate the design process utilizing industry-standard EDA tools to improve efficiency and analyze results
• Exhibit strong analytical and excellent communication skills, conceptual understanding, and attention to detail

Job Description – Logic Implementation

Logic Implementation involves synthesis and DFT where synthesis transforms RTL design into a gate-level netlist and DFT is an innovative design technique to make testing a chip cost-effective.

• Specify various constraints on the netlist, analyze Design Rule Constraints (DRCs), timing analysis of various timing paths and timing exceptions
• Work on bottom-up synthesis of hierarchical designs
• Generate the patterns to identify various faults in the design
• Insert the test logic and generate the patterns to detect the fault
• Work on understanding the various types of manufacturing defects that manifest during fabrication of the SOC and generate patterns to identify the same
• Understand the trade-offs for test time, test pattern size and test requirements
• Insert the JTAG TAP controller, test logic and test controls hierarchically into SOC design and run DFT design rule checks and analyze coverage reports
• Develop test patterns to test the SRAM memories, logic and GPIO using industry standard EDA tools
• Work closely with ATE test/Product engineering teams to bring up test patterns and debug post silicon issues
• Develop DFT mode timing constraints for physical design team to perform timing sign-off
• Exhibit strong analytical and excellent communication skills, conceptual understanding, and attention to detail

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