Job Description (IO Design) 
Minimum Qualification for “Engineer Trainee” position
- Eligibility: B.E./B.Tech/ M.Sc. in Electronics/ Electrical/ Instrumentation
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Candidates who are in the final semester are also eligible, provided they have no backlogs to date and no remaining classwork in their last semester at their college/university.
- Percentage: 65%
Job Description – IO Design
- Circuit Design & Modeling: Develop transistor-level circuits for GPIOs, including bidirectional buffers, level shifters, Schmitt-trigger inputs, pre-drivers, and pull-up/pull-down cells.
- Simulation & Verification: Perform comprehensive pre- and post-layout simulations using tools like HSPICE/Cadence to verify performance, signal integrity, and timing across PVT (Process, Voltage, Temperature) corners.
- Reliability & ESD: Design and simulate ESD (Electrostatic Discharge) protection structures, ensure Latch-Up immunity, and handle EM/IR (Electromigration/IR drop) analysis.
- Layout Coordination: Collaborate with Physical Design teams to implement area-efficient, compliant layouts.
- Silicon Validation: Support silicon debug and characterization in the lab to validate performance.
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