Careers in VLSI Design - Analog

Std. Cell Design

Job Description (Std.Cell Design)

Minimum Qualification for “Engineer Trainee” position

  • Eligibility: B.E./B.Tech/ M.Sc. in Electronics/ Electrical/ Instrumentation
  • Candidates who are in the final semester are also eligible, provided they have no backlogs to date and no remaining classwork in their last semester at their college/university.
  • Percentage: 65%

Job Description – Std.Cell Design

  • Specification & Definition: Defining the library components, including functionality (gates, flip-flops), drive strengths, voltage thresholds (VT options), and cell heights.
  • Schematic/RTL Design: Creating logic diagrams or RTL code for the cell function and performing simulation to verify logical correctness.
  • Layout Generation: Designing the physical layout of the transistors and interconnects using tools like Virtuoso, adhering to fixed cell heights and routing grids for automated placement.
  • Physical Verification (DRC/LVS): Running Design Rule Checks (DRC) to ensure foundry requirements and Layout vs. Schematic (LVS) to guarantee the layout matches the schematic.
  • Parasitic Extraction (PEX): Extracting parasitic resistance and capacitance (RC) to create a detailed netlist, which is used for realistic simulation.
  • Characterization: Running SPICE-level simulations on the verified layout to generate timing (delay), power, and functionality models (usually .lib format) for EDA tools. 


    Register Now* *For Info on future drives