Careers in VLSI Design - Analog

Memory Design

PROGRAM INFORMATION(Memory Design)

Program Duration

The program is offered in two different durations based on requirements, as indicated in the advertising posters.

  • Program-1 with 6-Month duration: Includes training along with project work.
  • Program-2 with 1-Year duration: The Program comprises a six-month training period followed by a six-month internship. Stipend will be provided during internship.

Training Fees

  • Sponsored Training: The entire training fee will be covered by the sponsoring company for candidates who have opted for sponsored training. However, the candidate must agree to the terms and conditions set by the sponsoring company.
  • Self-Sponsored Training: In special cases when it is provided as an option in the poster. The candidates who have chosen this option are required to pay the applicable training fees themselves.

Program Contents

  • Basic device physics: MOSFET, FDSOI, FinFET Operation
  • Combinational and Sequential circuit design at gate and functional block level and their stick diagrams
  • Fabrication process
  • OS: Unix
  • Scripting: PERL/Python, TCL, SKILL
  • Memory Introduction/Classification
  • Memory Physical Attributes
    • Words, Bits, Column Mux,
  • Memory Compiler Options and Floorplans
    • BIST, Redundancy, Power-Gating, Read/Write Assist
  • Critical Memory Blocks
    • Global/Local CONTROL/IO, Decoder, Column-Mux, Core Array
  • Bitcell Analysis
    • Bitcell Read/leak Current, AC/DC Write Margin, SNM
  • Design Checks
    • Analysis of Level Shifter, Power gating Switches, Core Bias
  • Memory Compiler TILER
  • Extraction Flow
  • Memory Compiler Characterization Flow
  • Bitcell Read/Write/ADM Margins
  • Logic Race Margins Overview
  • ESD circuits and Packaging
  • Verilog-D and Verilog-A
  • Industry Standard EDA tools
  • Advanced Technology Nodes

Program Logistics

  • Full Time, 6 months, 6 days per week
  • Lecture Sessions 3 hours per day
  • Lab & Design Practice 5 hours per day
  • 8:30am-9:00am: Student preparation
  • 9:00am-10:30am: Morning Lecture
  • 10:30am-01:00pm: lab /Assignment (with Tea Break)
  • 01:00pm-01:30pm: Lunch Break
  • 01:30pm-03:00pm: Afternoon Lecture
  • 03:00pm-06:00pm: lab /Assignment (with Tea Break)

 

Minimum Qualification for “Engineer Trainee” position

  • Eligibility: B.E./B.Tech/ M.Sc. in Electronics/ Electrical/ Instrumentation
  • Candidates who are in the final semester are also eligible, provided they have no backlogs to date and no remaining classwork in their last semester at their college/university.
  • Percentage: 65%

Minimum Qualification for “Jr. Engineer Trainee” position

  • Eligibility: Diploma in Electronics/ Electrical/ Communications/ IE or B.Sc. in Electronics
  • Percentage: 65%