Careers in VLSI Design - Analog

Memory Design

Job Description (Memory Design)

Minimum Qualification for “Engineer Trainee” position

Eligibility: B.E./B.Tech/ M.Sc. in Electronics/ Electrical/ Instrumentation
Candidates who are in the final semester are also eligible, provided they have no backlogs to date and no remaining classwork in their last semester at their college/university.
Percentage: 65%

Job Description – Memory Design

Memory design involves development and validation of Embedded SRAM/RF/ROM Memory IP

Specification and Architectural Design

Requirements Definition: Defining the target technology node (e.g., 7nm, 5nm), memory capacity (number of words and bits), power constraints, and performance requirements (speed).

Architecture Selection: Choosing the appropriate structure based on requirements, such as single-port, two-port, or dual-port memory.

Circuit Partitioning: Designing the hierarchical structure, such as partitioning a large array into smaller

banks to reduce word-line capacitance and improve speed

Circuit Design and Optimization (Leaf Cells)

Bit-cell Design: Designing the fundamental 6T (six-transistor) SRAM cell for high density (HD) or high speed (HS).

Peripheral Circuitry: Designing peripheral blocks, including address decoders, sense amplifiers, pre-charge circuits, and write drivers.

Optimization: Using techniques like dual-threshold transistors to optimize for low power (higher threshold) in memory core and high performance (lower threshold) in peripheral circuits.

Layout Generation and Verification

Physical Layout: Creating the physical layout for the memory bit cells and periphery, ensuring strict adherence to design rules (DRC) for the target process.

Layout Generation Strategy: Developing the script/TILER that connects the pre-designed “leaf cells” (bit cells, decoders) to create the full layout.

Verification: Performing layout-versus-schematic (LVS) checks to ensure the generated physical layout matches the circuit schematic.

Parasitic Modeling and Characterization

Parasitic Extraction: Extracting resistance and capacitance values from the layout to model real-world behavior.

Timing/Power Characterization: Simulating the design over different PVT (Process, Voltage, Temperature) corners to generate timing libraries (LIB), Verilog models, and power reports.

Verification of Timing: Analyzing read/write cycle timing, including Setup/Hold times, to ensure reliability.

Compiler Scripting and Integration

Generator Development: Writing the software code that automates the generation process. This script takes user input (e.g., ) and automatically places and routes the blocks to generate the final GDSII layout.

Compiler Interface: Creating the user interface (CLI or GUI) to input specifications such as memory size, aspect ratio, and port configuration.

Testing and Validation

Fabrication & Post-Silicon Testing: Fabricating test chips to verify the compiler’s output against the predicted performance metrics.

Yield Enhancement: Integrating test solutions like BIST (Built-in Self-Test) and repair circuits to improve yield.