Careers in VLSI Design - Analog

Circuit Layout / Package Layout (CLD)

Selection Process (Layout Design)

e selection and admission process for VEDA IIT programs involves three or four rounds, depending on the number of applications received.

  • Round 1: Preliminary Test – A one-hour screening test is conducted at the VEDA IIT campus in Hyderabad or at centers mentioned in the application form
  • Round 2: Main Test – Candidates who qualify in Round 1 will take a written test of two-hours duration at the VEDA IIT campus in Hyderabad or at centers mentioned in the application form.
  • Round 3: Technical & Personal Interview – Shortlisted candidates from the main test will undergo  technical and personal interviews at the VEDA IIT campus in Hyderabad.
  • Round 4: Optional based on sponsoring company requirements. 

The written exam will be of 3 hrs duration comprising of 1 mark,2marks, 3marks/4marks questions in the following pattern

  • Fill in the blanks
  • Short Answers Questions
  • Problems
Syllabus/Topics for Preliminary Test (Analog Domain) Marks# Duration

Basic Electronics (Basic RC Circuits, Diodes and BJTs) – 10M

Digital Design (Number Systems, Combinational Logic Circuits) – 10M

 20 1 hour
Aptitude 10
Topics for Main Test – Analog Design Domain Marks# Duration

Analog Design & Circuit Design

Analysis of Active and Passive circuits (BJT and MOSFET amplifiers: biasing, ac coupling, small signal analysis, frequency response, Current mirrors and differential amplifiers, Time and frequency domain analysis of linear circuits: RL, RC and RLC circuits), Opamp circuits: Amplifiers, summers, differentiators, integrators, active filters, Schmitt triggers and oscillators.

30

2 hours

Basic Electronics (Basic RC Circuits, Diodes and BJTs)

Kirchhoff’s Laws, Node and mesh analysis, superposition, Thevenin’s theorem, Norton’s theorem and maximum power transfer theorem, PN junction diode (clipping, clamping and rectifiers), Zener diode, BJT

10

Number Systems: Different radices/bases and its conversions, arithmetic operations on different radices, signed numbers: signed magnitude numbers, 1’s complement numbers, 2’s complement numbers
Digital Design
Combinational Logic Circuits: Minimization of Boolean functions, Logic gates, Multiplexers and De multiplexers , Decoders ,
Encoders, Priority Encoders, Comparators, Adders, Subtractors
Sequential Logic Circuits: Latches, Flip flops, Counters, Timing waveforms, Mealy & Moore State Diagrams, State tables

10

Aptitude: Area, Average, Boats and Streams, Calendar, Clock, Height and Distance, Logarithm, Logical Reasoning, Numericals and Numbers, Partnership, Percentage, Permutation and Combination, Pipes and Cistern, Probability, Problems on Ages, Problems on H.C.F and L.C.M, Problems on Trains, Profit and Loss, Races and Games, Ratio and Proportion, Square Root and Cube Root, Stocks and Shares, Time and Distance, Time and Work, True Discount, Volume and Surface Area

20

*Applicants need to bring their own pencils, pens, erasers etc. Question paper cum answer booklet will be provided at the center.
#Marks may vary slightly.