Careers in VLSI Design - Analog

IP Build & Validation

Job Description (IP Build & Validation)

Minimum Qualification for “Engineer Trainee” position

Eligibility: B.E./B.Tech/ M.Sc. in Electronics/ Electrical/ Instrumentation
Final‑semester students are also eligible, provided they have no backlogs and no pending coursework at the time of joining.
Minimum Percentage: 65%

Job Description – IP Build & Validation

IP Build & Validation engineers work on developing and validating semiconductor IPs to ensure they function correctly and meet performance, power, and reliability requirements before being used in complex SoC designs.

This role gives fresh graduates strong exposure to real industry IP development flows, EDA tools, and sign‑off practices, making it an excellent starting point for a VLSI career.

Key responsibilities include:

Build and validate Analog, Mixed‑Signal, or Digital IP Packages as per given scope committed to the customer.
Generate and check EDA views such as Liberty (.lib), Verilog, LEF, CDL, and GDS, which are required for SoC integration.
Validate IP behavior across different process, voltage, and temperature (PVT) corners.
Perform basic timing, power, and noise validation at the IP level.
Support SoC integration and customer teams by providing qualified IP deliverables and resolving issues.
Work closely with design, layout, and characterization teams to fix validation gaps.
Run sign‑off checks such as EM, IR, noise, and static timing analysis to ensure silicon reliability.
Learn and apply industry‑standard validation flows, methodologies, and automation techniques.

This role helps candidates build strong fundamentals in IP development, validation, and sign‑off, enabling growth into roles such as Senior Engineer, IP Validation Lead, Quality Engineer, Technical Lead, or Manager in the semiconductor industry.