Careers in VLSI Design - PV / CL

Physical Verification (PV)/ Layout Design (CLD)

Job Description (VLSI Design – Digital)

Minimum Qualification for “Engineer Trainee” position

  • Eligibility: B.E./B.Tech/ M.Sc. in Electronics/ Electrical/ Instrumentation
  • Candidates who are in the final semester are also eligible, provided they have no backlogs to date and no remaining classwork in their last semester at their college/university.
  • Percentage: 65%

Minimum Qualification for “Jr. Engineer Trainee” position

  • Eligibility: Diploma in Electronics/ Electrical/ Communications/ IE or B.Sc. in Electronics
  • Percentage: 70%

Job Description – Physical Verification

Physical verification is a process of verification of correct electrical and logical functionality, manufacturability, and yield in IC layout using EDA tools.

  • Perform various types of physical verification checks (such as LVS, DRC & Antenna, ERC, design-for-manufacturing & design-for-yield, and Pattern matching) at the chip and block level
  • Collaborate with the CAD/Technology teams for flow bring up and validation.
  • Work directly with the implementation team during the entire chip design cycle to drive signoff closure for tape-out
  • Automate the design process utilizing industry-standard EDA tools to improve efficiency and analyze results
  • Exhibit strong analytical and excellent communication skills, conceptual understanding, and attention to detail

    Job Description – Layout Design

    VLSI Layout is the process of designing an electronic circuit layout with the help of a layout
    editor. Electronic circuits can be Standard cells, Analog Circuits, Memory Circuits, IO Circuits, and Mixed Signal Circuits.

    • Job involves physical layout implementation of circuits and verification to comply with circuit specification requirements and to ensure high manufacturability
    • Use of advanced CAD tools and mask design knowledge to deliver correct and robust layouts that meet stringent constraints matching performance, area, and power requirements
    • Interpreting LVS, DRC, and ERC reports and debugging errors to find the fastest way to complete the layout having no violations
    • Good Understanding of reliability issues such as ESD, Electro migration & IR, and Latch-up
    • Skills to work with customer teams to deliver layouts in time that match target performance and area goals
    • The job requires strong analytical and excellent communication skills, conceptual understanding, and attention to detail

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