career readiness PROGRAMme IN VLSI ENGINEERING ( with fee )

career readiness Programme – Information

Program Contents

CORE Domain topics for LD, PD, AD, CLD* :

  • Topics in Digital Design
  • CMOS design concepts
  • Layout, stick diagrams, reverse Engineering
  • Fabrication
  • Unix Operating System, Shell Programming & VI Editor
  • Advanced Scripting Languages : PERL, TCL

* LD: Logic Design, PD: Physical Design, AD: Analog Design, CLD: Custom Layout Design

Domain specific topics for LD, PD, AD, CLD:

LOGIC DESIGN:

  • Introduction to Number system
  • Advanced Digital Design concepts
  • Coding designs in Verilog RTL and simulation
  • Unix Operating System, Shell Programming & VI Editor
  • Introduction to C & C++ Programming Languages
  • Advanced Scripting languages: PERL, TCL
  • Introduction to Synthesis
  • Introduction to Design For Test (DFT) – Scan, ATPG & JTAG Concepts (Institute Optional)
  • Introduction to Verification using System Verilog (Institute Optional)
  • Concepts of Static timing analysis (STA)
  • Transferable skills (Institute Optional)

PHYSICAL DESIGN:

  • Physical design flow
  • Floor plan & Power plan
  • Placement & Optimization
  • CTS, Routing
  • Extraction, STA & OCV
  • Signal Integrity
  • DFM
  • Power Grid analysis- IR, RJ & EM (Based on feasibility)
  • Low power design concepts (Based on feasibility)

ANALOG DESIGN:

  • Introduction to CMOS device operation
  • Introduction to Analog circuit design
  • Introduction to Circuit Analysis and Spice simulation
  • Nonlinear Networks and Load line analysis
  • Theory of operation of Differential Amplifiers
  • Analysis of Passive and Active Current Mirrors
  • Frequency Response of Amplifiers
  • Low frequency Operational Amplifiers
  • Introduction to Band Gap Reference circuit topologies
  • Unix Operating System, Shell Programming & VI Editor
  • Transferable skills (Institute Optional)

CUSTOM LAYOUT DESIGN:

  • Introduction to Layout Editors
  • Layouts of Basic Gates and Transmission Gates
  • Fingering and Parasitics
  • DRC/LVS
  • Process Antenna Effect
  • SPICE
  • Analog Devices and Matching
  • Analog Layout Guidelines and Key Points
  • Post Layout RC Extraction and Simulations
  • Training on appropriate tools and languages during labs

 

     

      Program Logistics

      • Full Time, 6 months, 6 days per week
      • Lecture Sessions 3 hours per day
      • Lab & Design Practice 5 hours per day
      • 9:00am-10:30am: Morning Lecture
      • 10:30am-01:00pm: lab /Assignment (with Tea Break)
      • 01:00pm-01:30pm: Lunch Break
      • 01:30pm-03:00pm: Afternoon Lecture
      • 03:00pm-06:30pm: lab /Assignment (with Tea Break)