Job Title and Job Description

in VLSI Design/ Embedded System Design/ Applied Ai

Domains – VLSI Design-VLSID/Embedded System Design-ESD, Applied AI

Job titles and Job Description

  • Engineer Trainee in the 1st year and Engineer-1 in the 2nd year.
  • VLSI Engineering includes the following domains that will have further sub-domains
  • VLSI Logic Design (RTL): Logic design entails working with a high-level architecture specification of the product and coming up with the micro-architecture specification, converting the micro-architecture specification into efficient Verilog RTL code, at IP or SOC level. Designers need to work at the SoC level to integrate the various IP blocks and tune the architecture to meet the performance requirements of the product and also closely work with DV engineers to help fix the bugs and solve any issues that arise during the design cycle.
  • VLSI Digital Verification (DV): Digital Verification domain deals with verifying the correctness of the functionality of a given design against its specification. The verification Cycle mainly includes Test Plan, Test Stimulus, Test bench, Coverage development, DV Metrics Closure, and DV Signoff. It is performed at various levels like IP, Subsystem, SOC, and Multi-Chip SOC. RTL or Gate level Simulation, Emulation, and Formal Verification are some of the techniques involved in DV.
  • VLSI Physical Design (PD): Physical design is a process of converting logical connectivity of cells (netlist) into physical connectivity (manufacturable layout) meeting power, performance, and area requirements. All design components are instantiated with their geometric shapes and have appropriate routing connections in metal layers. This involves Physical Placement & Routing, Functional Equivalence, Timing Closure, Verification of correct electrical and logical functionality of physical design vs logic design, manufacturability, and yield using EDA tools before the design is taped-out for semiconductor fabrication.
  • VLSI Design Implementation (DI):  Design implementation involves the conversion of high-level design intent specified in RTL to logical gates known as Synthesis, and the development of timing constraints to help Physical design engineers close the timing/performance targets. The implementation also entails the insertion of Design For Test (DFT) structures to help test the design post-fabrication for any manufacturing defects. Complex submicron designs with billions of logic gates and multiple MB of memory are tested using DFT in a fraction of the time compared to exhaustive functional verification tests.
  • Embedded Software Development (ESW): The engineer is responsible for the design and development of embedded software consisting of device drivers, Algorithms implementation of the DSP and RISC processors, understanding the RTOS concepts and developing the functions meeting the real-time constraints. This domain requires an understanding of CISC/RISC processor and Microcontroller architectural features, the functionality of standard peripheral controllers, and equipped with proficient programming skills in C and Assembly languages, and RTOS
  • VLSI Analog Design (AD): Analog design is the front-end activity of developing an Analog IP or block with circuit designs that operate in and are optimized for continuous time-domain behaviour.  Analog circuit includes Amplification, Processing, Conversion, and Filtering. Analog design generally involves the top (system level) to the bottom (transistor level) approach.
    • Implement a fully functional block to meet the given specifications using macroblocks such as Amplifiers, Filters, Comparators, etc.
    • Design of standard Analog IPs like ADC, DAC, PLL, Oscillator, Voltage regulator, General purpose and Special IO, Serial Protocol IPs like SerDes, DPHY, USB, etc., for high performance with the minimum area and low power.
    • Design Full-custom circuits for memory arrays like multi-port register files, SRAMs, and/or caches for performance-critical IPs like CPUs/GPUs.
    • Run sign-off checks by running various flows like EM, IR, noise, and static timing analysis.
    • Support to Validation for SoC Applications teams and further to the end customers.
  • VLSI IO Design:
    • IO Design involves developing transistor-level circuits for GPIOs, including bidirectional buffers, level shifters, Schmitt-trigger inputs, pre-drivers, and pull-up/pull-down cells.
    • Performing comprehensive pre- and post-layout simulations using tools like HSPICE/Cadence to verify performance, signal integrity, and timing across PVT (Process, Voltage, Temperature) corners.
    • Designing and simulating ESD (Electrostatic Discharge) protection structures, ensure Latch-Up immunity, and handle EM/IR (Electromigration/IR drop) analysis.

    Collaborating with Physical Design teams to implement area-efficient, compliant layouts.

  • VLSI STD CELL Design & Layout:
    • STDCELL Design involves defining the library components, including functionality (gates, flip-flops), drive strengths, voltage thresholds (VT options), and cell heights.
    • Creating logic diagrams or RTL code for the cell function and performing simulation to verify logical correctness.
    • Designing the physical layout of the transistors and interconnects using tools like Virtuoso, adhering to fixed cell heights and routing grids for automated placement.
    • Running Design Rule Checks (DRC) to ensure foundry requirements and Layout vs. Schematic (LVS) to guarantee the layout matches the schematic.
    • Running SPICE-level simulations on the verified layout to generate timing (delay), power, and functionality models (usually .lib format) for EDA tools.
  • VLSI MEMORY Design & Layout:
    • Memory design involves development and validation of Embedded SRAM/RF/ROM Memory IP, as per target technology node (e.g., 7nm, 5nm), memory capacity (number of words and bits), power constraints, performance requirements (speed), and the structure like single-port, two-port, or dual-port memory.
    • Partitioning a large array into smaller banks to reduce word-line capacitance and improve speed, designing the fundamental 6T (six-transistor) SRAM cell for high density (HD) or high speed (HS).
    • Designing peripheral blocks, including address decoders, sense amplifiers, pre-charge circuits, and write drivers. Using techniques like dual-threshold transistors to optimize for low power (higher threshold) in memory core and high performance (lower threshold) in peripheral circuits.
    • Creating the physical layout for the memory bit cells and periphery, ensuring strict adherence to design rules (DRC) for the target process.
    • Developing the script/TILER that connects the pre-designed “leaf cells” (bit cells, decoders) to create the full layout. layout-versus-schematic (LVS) checks to ensure the generated physical layout matches the circuit schematic. Extracting resistance and capacitance values from the layout to model real-world behavior.
    • Simulating the design over different PVT (Process, Voltage, Temperature) corners to generate timing libraries (LIB), Verilog models, and power reports.
  • VLSI Custom Layout Design (CLD): Custom layout is the process of designing an electronic circuit layout with the help of a layout editor. Electronic circuits can be Standard cells, Analog Circuits, Memory Circuits, IO Circuits, and Mixed Signal Circuits.
    • Job involves physical layout implementation of circuits and verification to comply with circuit specification requirements and to ensure high manufacturability
    • Use of advanced CAD tools and mask design knowledge to deliver correct and robust layouts that meet stringent constraints matching performance, area, and power requirements
    • Interpreting LVS, DRC, and ERC reports and debugging errors to find the fastest way to complete the layout having no violations
    • Good Understanding of reliability issues such as ESD, Electro migration & IR, and Latch-up
    • Skills to work with customer teams to deliver layouts in time that match target performance and area goals
    • The job requires strong analytical and excellent communication skills, conceptual understanding, and attention to detail
  • IC Package Design and Layout: Package design and layout engineering involves defining and implementing physical layouts for IC packages such as wire-bond, flip-chip, BGA, wafer-level, 2.5D/3D and chiplet-based packages.
    At the entry level, engineers will support package floor-planning, die and bump placement, substrate routing, stack-up definition, power/ground planning, signal integrity awareness, and design-rule compliant layout implementation using industry-standard EDA/CAD tools. The role includes assisting with electrical, thermal, and mechanical design checks; reviewing DRC/LVS-style package verification reports where applicable; preparing design documentation; and working closely with silicon design, package technology, signal integrity, power integrity, reliability, and manufacturing teams to deliver manufacturable, reliable, and cost-effective package solutions. The role requires strong fundamentals in electronics – high-speed transmission lines, impedance matching, crosstalk reduction, and insertion/return loss etc.,
  • IP Build & Validation:
    • IP Build & Validation involves building, checking, and qualifying semiconductor IP deliverables before production release.
    • The engineer works with Foundation IP products such as standard-cell libraries, I/O libraries, memory compilers, and mixed-signal IP to ensure that generated views, models, and release packages are complete, consistent, and compliant with defined specifications and quality requirements.
    • Validate the functional, timing, physical, and data consistency of generated views, including Liberty, Verilog/VHDL, LEF, GDS/OASIS, and CDL/SPICE, and perform compilation, simulation, syntax and format checks, and cross-view checks.
    • Review physical-verification results, including DRC, LVS, ERC, antenna, density, and reliability checks.
    • Execute PNR QA, mimicking the RTL-GDSII flow, to ensure that the collaterals are compliant with industry-standard implementation tools.
    • Perform package-level quality checks, including file integrity, naming conventions, required-view completeness, version consistency, checksums, and documentation review.
    • Develop and enhance scripts, regression tests, dashboards, and automation using languages such as Python, Tcl, Shell, or Perl.
  • Methodology & Flow Strategy:
    • Technology: Engineers will learn & support towards the PDK Enablement for basic collaterals like DRC, LVS, followed by deeply understanding and performing the assessments on the impacts of the changes over the versions & sometimes nodes. On FE side will be more focused on any simulation-based analysis of the technology such as running Device-level, RO-level or BitCell-level FOM studies. The role requires strong fundamental understanding of CMOS device physics, including advanced architectures like GAA (Gate-All-Around) and FinFETs. Also, knowledge of Layout Versus Schematic (LVS), Design Rule Checking (DRC), Parasitic Extractions, and Spice models at transistor level is must.
    • Modelling: FW Modeling  requires developing, validating, maintaining, and supporting frontend models for Standard Cells, Memory and GPIO & MSIP products. FE models include Verilog Simulation Models (using various modeling styles, constructs, UDPs, and behavioral abstractions), ATPG Models (pattern generation, logic simulation, and DFT validation), BIST-related Models, CTL Models for scan and test-related flows, UPF/CPF Low-power Models (representing the power behavior and power intent of IPs), Emulation & Verilog-RTL, and Emulator Model. Lib Modelling requires working on enabling Liberty Model for Standard Cell IPs, enabling the new functionalities, new features across all the technology nodes. It includes managing & validating the templates, methodologies and flows which are to be used, performing regular regressions and supporting the production team in debugging the issues.  The role requires strong fundamental understanding of CMOS device physics, including advanced architectures like GAA (Gate-All-Around) and FinFETs, Digital Electronics and Verilog Language. Also, decent knowledge of spice simulator and logic simulator (Verilog) is must.
    • EDA  collaboration bridges the gap between EDA and Design worlds, requiring to work based on specific tool related market needs and IP Design Teams work based on what IP users need. This collaboration happens for all the flow parts involving multiple different tools such as Liberate, Spectre, Xcellium, Palladium, Innovus, Genus, Modus, etc. . This gives a good overview of the complete flow from Design to end implementation to the team, which helps them grow and think analytically what can impact where.